DBLX=DBLX_0, DBLEN=DBLEN_0, LDMOD=LDMOD_0, SPLIT=SPLIT_0, COMPMODE=COMPMODE_0, LDFQ=LDFQ_0, HALF=HALF_0, FULL=FULL_0, PRSC=PRSC_0
Control Register
| DBLEN | Double Switching Enable 0 (DBLEN_0): Double switching disabled. 1 (DBLEN_1): Double switching enabled. |
| DBLX | PWMX Double Switching Enable 0 (DBLX_0): PWMX double pulse disabled. 1 (DBLX_1): PWMX double pulse enabled. |
| LDMOD | Load Mode Select 0 (LDMOD_0): Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 1 (LDMOD_1): Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. |
| SPLIT | Split the DBLPWM signal to PWMA and PWMB 0 (SPLIT_0): DBLPWM is not split. PWMA and PWMB each have double pulses. 1 (SPLIT_1): DBLPWM is split to PWMA and PWMB. |
| PRSC | Prescaler 0 (PRSC_0): PWM clock frequency = fclk 1 (PRSC_1): PWM clock frequency = fclk/2 2 (PRSC_2): PWM clock frequency = fclk/4 3 (PRSC_3): PWM clock frequency = fclk/8 4 (PRSC_4): PWM clock frequency = fclk/16 5 (PRSC_5): PWM clock frequency = fclk/32 6 (PRSC_6): PWM clock frequency = fclk/64 7 (PRSC_7): PWM clock frequency = fclk/128 |
| COMPMODE | Compare Mode 0 (COMPMODE_0): The VAL* registers and the PWM counter are compared using an “equal to” method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 1 (COMPMODE_1): The VAL* registers and the PWM counter are compared using an “equal to or greater than” method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. |
| DT | Deadtime |
| FULL | Full Cycle Reload 0 (FULL_0): Full-cycle reloads disabled. 1 (FULL_1): Full-cycle reloads enabled. |
| HALF | Half Cycle Reload 0 (HALF_0): Half-cycle reloads disabled. 1 (HALF_1): Half-cycle reloads enabled. |
| LDFQ | Load Frequency 0 (LDFQ_0): Every PWM opportunity 1 (LDFQ_1): Every 2 PWM opportunities 2 (LDFQ_2): Every 3 PWM opportunities 3 (LDFQ_3): Every 4 PWM opportunities 4 (LDFQ_4): Every 5 PWM opportunities 5 (LDFQ_5): Every 6 PWM opportunities 6 (LDFQ_6): Every 7 PWM opportunities 7 (LDFQ_7): Every 8 PWM opportunities 8 (LDFQ_8): Every 9 PWM opportunities 9 (LDFQ_9): Every 10 PWM opportunities 10 (LDFQ_10): Every 11 PWM opportunities 11 (LDFQ_11): Every 12 PWM opportunities 12 (LDFQ_12): Every 13 PWM opportunities 13 (LDFQ_13): Every 14 PWM opportunities 14 (LDFQ_14): Every 15 PWM opportunities 15 (LDFQ_15): Every 16 PWM opportunities |